Designing a Datapath from an FPGA to a Processor with SoC Blockset: Modeling and Simulation
This video walks through a a systematic approach to designing the datapath between the hardware logic of an FPGA and an embedded processor using SoC Blockset™. Applications are often partitioned between hardware logic and an embedded processor on a system-on-chip (SoC) device to meet throughput, latency, and processing requirements.
Learn to design and simulate an entire application comprising FPGA and processor algorithms along with memory interfaces. You will see how to use blocks from SoC Blockset to model shared external memory, and how to use SoC Blockset to measure different forms of latency, and data loss from memory buffers.
By performing these analyses using simulation, you have better visibility into your design than when working with just hardware. You can uncover issues like loss of throughput, latency, and dropping of samples before implementing on hardware.
View example: https://bit.ly/2YYzzRN
Learn to design and simulate an entire application comprising FPGA and processor algorithms along with memory interfaces. You will see how to use blocks from SoC Blockset to model shared external memory, and how to use SoC Blockset to measure different forms of latency, and data loss from memory buffers.
By performing these analyses using simulation, you have better visibility into your design than when working with just hardware. You can uncover issues like loss of throughput, latency, and dropping of samples before implementing on hardware.
View example: https://bit.ly/2YYzzRN
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