Design Multiple-Pixel-Per-Clock FPGA Applications

Processing multiple pixels per clock in parallel enables FPGA and ASIC hardware to process 4k, 8k, or high-frame-rate video streams. Vision HDL Toolbox™ natively supports multi-pixel-per-clock processing. Its Frame-to-Pixels and Pixels-to-Frame gateway blocks offer easy settings to switch the design’s inputs and outputs from one pixel at a time to 4 or 8 in parallel, and its built-in blocks such as image filtering and edge detection natively support this mode. To develop custom multi-pixel-per-clock algorithms, the Line Buffer block in Vision HDL Toolbox stores enough rows to form the neighborhood size you specify and outputs columns and control signals for 1, 4, or 8 pixels at a time. The design shown is a custom implementation of the example from this video (https://bit.ly/2kW3g48) that uses built-in blocks. It shows how to use the Line Buffer to create four parallel neighborhood windows to be processed by a custom-designed image filter and edge detector. The parallel windows overlap significantly, so the design is architected to share these hardware resources. Finally, it discusses hardware micro-architecture considerations such as register pipeline insertion and approaches to reduce multiplier usage while meeting latency requirements.