FPGA Design with MATLAB, Part 5: Generating and Synthesizing RTL

FPGA programming traditionally starts with providing register transfer level (RTL) VHDL® or Verilog® code to an FPGA synthesis tool. In this part of the tutorial we will show how to automatically generate RTL from the verified high-level architectural model, analyze estimated timing and resource usage, and then automatically run synthesis.

This video covers:

- Running checks for HDL code generation readiness and potential hardware inefficiencies
- Resolving the reported issues automatically or manually
- Setting up third-party tools to synthesize the generated VHDL or Verilog
- The stages, tasks, and settings for generating RTL code using the HDL Workflow Advisor
- Resource usage and optimization report, which provides fast high-level feedback before moving on to synthesis
- Analysis of the timing and critical path from FPGA synthesis


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