MATLAB-to-SystemC Workflow for Cadence Stratus HLS

 The MATLAB-to-SystemC workflow for Cadence Stratus HLS involves the following steps:

• Create a MATLAB model: First, you need to create a MATLAB model of the system that you want to implement in hardware using Cadence Stratus HLS. This model should be a high-level representation of the system that includes all the necessary algorithms and functional requirements.

• Generate RTL code from MATLAB: The next step is to use MATLAB Coder to generate RTL code from the MATLAB model. MATLAB Coder is a tool that automatically generates C or C++ code from MATLAB code. In this case, it will generate RTL code that can be used by Cadence Stratus HLS.

• Import the RTL code into Cadence Stratus HLS: Once you have the RTL code, you can import it into Cadence Stratus HLS. This can be done using the Import IP feature in Stratus HLS. Import IP allows you to import external RTL code into your Stratus HLS project.

• Perform HLS optimization: After importing the RTL code, you can use Stratus HLS to perform high-level synthesis (HLS) optimization on the code. This step involves refining the RTL code to improve its performance, area, power consumption, and other parameters.

• Simulate and verify the design: Once you have optimized the RTL code using Stratus HLS, you can simulate and verify the design. This step involves running simulations to ensure that the hardware implementation of the system is correct and meets the functional requirements.

• Export the SystemC code: After verifying the design, you can export the SystemC code from Stratus HLS. SystemC is a high-level hardware description language that is commonly used for hardware design and verification.

• Perform RTL synthesis and place-and-route: Finally, you can use the SystemC code to perform RTL synthesis and place-and-route using a tool like Cadence Genus Synthesis and Cadence Innovus Implementation System, respectively. These tools will generate the final hardware implementation of the system.

Overall, this MATLAB-to-SystemC workflow provides a streamlined process for designing and implementing hardware systems using Cadence Stratus HLS.

Watch a step-by-step demonstration of how to use HDL Coder™ with the Cadence® Stratus™ HLS high-level synthesis tool to create highly optimized ASIC implementations of MATLAB® code. The demo features a floating-point, least-mean squares (LMS) digital filter in MATLAB. The HDL Coder workflow is used to generate fixed-point MATLAB code, from which HDL Coder can generate synthesizable SystemC™ code along with a SystemC testbench using simulation. Then Stratus HLS is used to explore alternative ASIC implementations.

- SystemC Code Generation from MATLAB: https://bit.ly/43T7Y34