From Algorithms to FPGA / ASIC Implementation with MATLAB and Simulink

 Learn about generating HDL code from MATLAB® code and Simulink® models for FPGA and ASIC implementation. This session starts with a brief introduction to Model-Based Design and the hardware development workflow. A MathWorks engineer will then demonstrate the step-by-step process with HDL Coder™ to start from initial models, incorporate hardware-specific constructs, and generate Verilog and VHDL code for FPGAs and ASICs.

Highlights

- Using Simulink and Model-Based Design for hardware development.

- Converting floating point to fixed point for hardware implementation

- Incorporating MATLAB code into HDL workflows using Simulink

- Prototyping designs on FPGA and SoC development boards

- Request trial: https://bit.ly/3CJW66D

- Learn about FPGA and ASIC Design with HDL Coder: https://bit.ly/3IDqRgq

Chapters: 

00:00 Background / motivation

03:28 SoC collaboration with Model-Based Design

04:22 Overview of HDL Coder

10:38 Description of pulse detector example

11:38 Developing the streaming Simulink model

21:08 Testbench for streaming model

24:01 Modeling for HDL code generation

27:49 Specify hardware microarchitectures

24:19 Fixed-point quantization concepts

37:07 Fixed-point in MATLAB and Simulink 

39:42 Performing fixed-point operations 

40:45 Managing fixed-point in Simulink models 

43:15 What is the Fixed-Point Tool for? 

45:05 Simulink model with fixed-point blocks

46:20 How to use the Fixed-Point Tool 

49:59 Generating HDL code 

52:15 Synthesis and programming 

53:02 Designing for other FPGA targets 

54:44 Hardware deployment 

55:37 Conclusion